The present invention relates generally to interface circuits and more specifically for a circuit interfacing transistor to transistor logic (TTL) to complementary metal oxide semiconductor (CMOS) insulated gate field effect transistor circuits.
As is well known, there is difficulty in interfacing a TTL circuit which has the designed voltage variation of 0.8 to 2.0 volts with CMOS circuits which are designed for voltage variations in the range of 0 to approximately 15 volts. One class of interface circuits has used ratioed CMOS inverters as the output drive circuit. These inverters are generally slow and must drive high capacitive loads. One method of increasing the speed of the interface circuit is described in U.S. Pat. No. 3,900,746 to Kraft et al. A divertable current sink in the form of a third field effect transistor is connected in series with the inverter. Although Kraft et al is an improvement over prior art inverter outputs, these series connections of the current sink with the inverter's N channel device on the output provides a resistance which limits the response time of the inverter.
Although most output inverters will switch between the high and low voltage signal required in CMOS logic, the operating point about which they switch may vary considerably. This results from many factors including primarily manufacturing mismatch between the P and N channel devices. In the ideal situation, it is preferred that the output voltage be in the center of the output voltage swing when the input voltage is in the center of the input voltage swing. Thus the operating point should be the mid-point of the input voltage swing. One method of compensating a CMOS inverter for variations is to include variable resistive elements in series with the P channel device and in series with the N channel device which may be controlled inversely to each other to reach a balance. This method is illustrated in U.S. Pat. No. 3,914,702 to Gehweiler. Although Gehweiler improves the accuracy of the operating point of the inverter, it adds resistance to each of the current paths and thus consequently slows the response time of the inverter.
Thus, there exists a need for an interface circuit using a CMOS inverter as the output stage which has a fixed operating point and improved response time.